The present application is directed to the configuration of semiconductor based devices and more particularly to configuring semiconductor based devices such as Thin Film Transistors (TFTs) with an increased current flow.
A typical existing TFT structure 100 is shown in FIG. 1, and consists of a stack including an insulator 102 and semiconductor 104 deposited over a plane (or planar) gate electrode 106. The source electrode 108 and drain electrode 110 are deposited over semiconductor 104 with doping at the contacts, and some overlap between the source and drain electrodes and gate electrode 106 to ensure low contact resistance.
Thin film transistors (TFTs) based on non-crystalline semiconductors are of interest for a number of uses including but not being limited to large area electronics. In some of these implementations TFTs are employed as access switches, such as for electronic based pixel configurations. For these and other uses it is preferable to have a fast turn on of the TFTs to improve access speed. It is understood that the turn on speed of TFTs may be increased by increasing currents in the TFTs.
In order to attain higher currents in existing TFTs structures, there are two passive approaches. The first is to increase the aspect ratio of the TFTs. In one instance, the aspect ratio may be increased by increasing channel width, which is at the cost of parasitic capacitance. The second approach to increase the aspect ratio would be to reduce channel length. The second passive approach to attain higher currents is to increase the dielectric capacitance. If the dielectric coefficient remains unchanged this is accomplished by making the dielectric thin. Such an approach comes with the cost of creating pinholes in the device structure.
It is therefore considered beneficial to provide a TFT configuration that improves the current flow as a way to achieve fast TFT turn on, and which overcomes at least some of the issues in existing approaches.